Fifteen Years of Formal Property Verification in Intel
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چکیده
Model checking technologies have been applied to hardware verification in the last 15 years. Pioneering work has been conducted in Intel since 1990 using model checking technologies to build industrial hardware verification systems. This paper reviews the evolution and the success of these systems in Intel and in particular it summarizes the many challenges and learning that have resulted from changing how hardware validation is performed in Intel to include formal property verification. The paper ends with a discussion on how the learning from hardware verification can be used to accelerate the industrial deployment of modelchecking technologies for software verification. Since 1995 Intel engineers have been using formal verification tools to verify properties of hardware designs. The first generation of Intel formal property verification tools [1, 2, 3, 4, 5, 6], called Prover, included an enhanced version of SMV, the BDDbased model checker developed by Ken McMillan [17], and a specification language, called FSL, that was an hardware linear temporal language inspired by LTL, the linear temporal logic proposed by Pnueli [18]. The compiler for FSL translated the linear logic into automata using algorithms similar to [19]. FSL was used both to specify formal properties to be verified by the model checker and to specify checkers to be checked dynamically during simulation of the hardware designs. Two lead CPU design teams used Prover for 1995 till 1999. Both teams reported successful usage of the new verification technology and in particular high quality
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تاریخ انتشار 2008